|[ Team LiB ]|
Memory speed is one of the most important factors in determining the speed of a computer. If a microprocessor cannot get the data and program code it needs, it has to wait. Using the right kind of memory and controlling it effectively are both issues governed by the chipset.
Handling memory for today's chipsets is actually easier than a few years ago. When computer-makers first stated using memory caches to improve system performance, they thrust the responsibility for managing the cache on the chipset. But with the current generation of microprocessors, cache management has been integrated with the microprocessor. The chipset only needs to provide the microprocessors access to main memory through its system bus.
To a microprocessor, accessing memory couldn't be simpler. It just needs to activate the proper combination of address lines to indicate a storage location and then read its contents or write a new value. The address is a simple binary code that uses the available address lines, essentially a 64-bit code with a Pentium-level microprocessor.
Unfortunately, the 64-bit code of the microprocessor is completely unintelligible to memory chips and modules. Semiconductor-makers design their memory chips so that they will fit any application, regardless of the addressing of the microprocessor or even whether they link to a microprocessor. Chips, with a few megabytes of storage at most, have no need for gigabyte addressability. They need only a sufficient number of addresses to put their entire contents—and nothing more—online.
Translating between the addresses and storage format used by a microprocessor and the format used by memory chips and modules is the job of the memory decoder. This chip (or, in the case of chipsets, function) determines not only the logical arrangement of memory, but also how much and what kind of memory a computer can use.
The memory functions of modern chipsets determine the basic timing of the memory system, controlling which signals in the memory system are active at each instant for any given function. The ability to adjust these timing values determines the memory technology that a computer can use. For example, early chipsets timed their signals to match Synchronous Dynamic Random Access Memory (SDRAM) memory chips. High-performance chipsets need to address Rambus memory and double-data rate memory, which use not only a different addressing system but also an entirely different access technology.
In addition, the chipset determines how much memory a computer can possibly handle. Although a current microprocessor such as the Pentium 4 can physically address up to 64GB of memory, modern chipsets do not support the full range of microprocessor addresses. Most current Intel chipsets, for example, address only up to 2GB of physical memory. Not that Intel's engineers want to slight you—they have not purposely shortchanged you. The paltry memory capacity is a result of physical limits of the high-speed memory buses. The distance that the signals can travel at today's memory speed is severely limited, which constrains how many memory packages can fit near enough to the chipset. Intel actually provides two channels on its Rambus chipsets, doubling the capacity that otherwise would be available through a Rambus connection.
Most memory chips that use current technologies require periodic refreshing of their storage. That is, the tiny charge they store tends to drain away. Refreshing recharges each memory cell. Although memory chips handle the process of recharging themselves, they need to coordinate the refresh operation with the rest of the computer. Your computer cannot access the bits in storage while they are being refreshed.
The chipset is in charge of signaling memory when to refresh. Typically the chipset sends a signal to your system's memory at a preset interval that's chosen by the computer's designer. With SDRAM memory and current chipsets, the refresh interval is usually 15.6 microseconds.
Memory can also self-refresh, triggering its own refresh when necessary. Self-refresh becomes desirable when a system powers down to one of its sleep modes, during which memory access is suspended along with microprocessor operation, and even the major portions of the chipset switch off. Operating in this way, self-refresh preserves the contents of memory while reducing the power required for the chipset.
Early personal computers relied on simple error detection, in which your computer warned when an error changed the contents of memory (unfortunately "warning" usually meant shutting down your computer). Current systems use an error-correction code (ECC), extra information added to that sent into memory through which the change of a stored bit can be precisely identified and repaired. The chipset adds the ECC to the data sent to memory, an extra eight bits for every eight bytes of data stored. When the chipset later reads back those eight bytes, it checks the ECC before passing the bytes on to your microprocessor. If a single bit is in error, the ECC identifies it, and the chipset restores the correct bit. If an error occurs in more than one bit, the offending bits cannot be repaired, but the chipset can warn that they have changed.
ECC is a programmable feature of most chipsets. Depending on the design of your computer, it can be permanently set on or off at the factory, or you may be able to switch it on and off through your system's advanced setup procedure. Simply switching ECC on doesn't automatically make your computer's memory more secure. An ECC system requires that your computer have special ECC memory modules installed.
|[ Team LiB ]|